The dimensions of many different types of state of the art electronic devices are ever decreasing. To reduce the dimensions of electronic devices, the structures by which the microprocessors, memory devices, other semiconductor devices, and other electronic componentry of these devices are packaged and assembled with circuit boards must become more compact.
One approach to reducing the sizes of assemblies of semiconductor devices and circuit boards has been to minimize the profiles of the semiconductor devices or other electronic components upon carrier substrates (e.g., circuit boards) to which the semiconductor devices are electrically connected so as to reduce the distances the semiconductor devices protrude from the carrier substrates. Various types of packaging technologies have been developed to facilitate orientation of semiconductor devices upon carrier substrates in this manner.
One example of such a technology is the so-called “flip-chip,” or controlled collapse chip connection (C-4), technology. In flip-chip technology, the bond pads or contact pads of a semiconductor device are arranged in an array over a major surface of the semiconductor device. Flip-chip techniques are applicable to both bare and packaged semiconductor devices. A packaged flip-chip type semiconductor device, which typically has a “ball grid array” (BGA) connection pattern, typically includes a semiconductor die and a substrate element, which is typically termed an “interposer.” The interposer may be disposed over either the backside of the semiconductor die or the front (active) surface thereof.
When the interposer is positioned adjacent the backside of the semiconductor die, the bond pads of the semiconductor die are typically electrically connected by way of wire bonds or other intermediate conductive elements to corresponding contact areas on a top surface of the interposer. These contact areas communicate with corresponding bumped contact pads on the backside of the interposer. This type of flip-chip assembly is positioned adjacent to a carrier substrate with the backside of the interposer facing the carrier substrate.
If the interposer is positioned adjacent the active surface of the semiconductor die, the bond pads of the semiconductor die may be electrically connected to corresponding contact areas on an opposite, top surface of the interposer by way of intermediate conductive elements that extend through one or more holes formed in the interposer. Again, the contact areas communicate with corresponding bumped contact pads on the interposer. In this type of flip-chip semiconductor device assembly, however, the contact pads are also typically located on the top surface of the interposer. Accordingly, this type of flip-chip assembly is positioned adjacent a carrier substrate by orienting the interposer with the top surface thereof facing the carrier substrate.
In each of the foregoing types of flip-chip semiconductor devices, the contact pads of the interposer are disposed in an array that has a footprint that mirrors an arrangement of corresponding terminals formed on a carrier substrate. Each of the bond pads (on bare flip-chip semiconductor dice) or contact pads (on flip-chip packages) and its corresponding terminal may be electrically connected to one another by way of a conductive structure, such as a solder ball, that also spaces the interposer some distance away from the carrier substrate.
The space between the interposer and the carrier substrate may be left open or filled with a so-called “underfill” dielectric material that provides additional electrical insulation between the semiconductor device and the carrier substrate.
In addition, each of the foregoing types of flip-chip type semiconductor devices may include an encapsulant material covering portions or substantially all of the interposer and/or the semiconductor die.
Another approach to reducing the sizes of assemblies of semiconductor devices and carrier substrates has been to reduce the amount of “real estate,” or surface area, upon a carrier substrate that is consumed by individual semiconductor device packages. This is typically done by reducing the dimensions of the semiconductor device packages along a plane that is parallel to a plane of the substrate upon which the semiconductor device packages are to be carried. As a result of ever-decreasing package dimensions, the so-called “chip-scale package” (CSP) has been developed. The dimensions of the outer peripheries of chip-scale packages are typically substantially the same as or only slightly larger than the corresponding dimensions of the outer peripheries of the semiconductor dice that are used in chip-scale packages.
As indicated previously herein, some chip-scale packages have ball grid array connection patterns. Some ball grid array chip-scale packages include interposers that are configured to be secured over the active surfaces of semiconductor dice, with bond pads of the dice being exposed through an opening formed through the interposer. Due to the limited dimensions of chip-scale packages, the dimensions of the interposers for use therein are also constrained, as are the sizes of openings formed through the interposers. In addition, state of the art semiconductor dice typically include bond pads that are positioned very near the outer peripheries of the dice. Consequently, in order to maintain the structural integrity of chip-scale package interposers, the interposer openings may not extend a sufficient lateral distance beyond bond pads of their corresponding semiconductor devices to provide adequate clearance for the tip of a wire bonding capillary or other intermediate conductive element-forming, -positioning, or -securing apparatus to properly access the bond pads.
Accordingly, there is a need for a chip-scale package interposer that includes an opening which is configured to facilitate access to bond pads located at or near the edges of semiconductor dice by apparatus for forming, positioning, or securing intermediate conductive elements. There is also a need for a method for fabricating such interposers.